Top 10 similar words or synonyms for deasserting

deassertion    0.816572

deasserts    0.756954

drdy    0.727191

unasserted    0.721045

txen    0.715624

txdisable    0.714250

stpclk    0.711971

trdy    0.711727

intrq    0.710287

rstb    0.709835

Top 30 analogous words or synonyms for deasserting

Article Example
Conventional PCI The target requests the initiator end a burst by asserting STOP#. The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction. There are several ways for the target to do this:
Conventional PCI The only minor exception is a "master abort termination", when no target responds with DEVSEL#. Obviously, it is pointless to wait for TRDY# in such a case. However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#. (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.) This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.
Conventional PCI On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#. This is known as "master abort termination" and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case. PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.
Conventional PCI The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again. The master may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.
Three-state logic When chip select is asserted, the chip internally performs the access, and only the final output drivers are disabled by deasserting output enable. This can be done while the bus is in use for other purposes, and when output enable is finally asserted, the data will appear with minimal delay. A ROM or static RAM chip with an output enable line will typically list two access times: one from chip select asserted and address valid, and a second, shorter time beginning when output enable is asserted.
MOS Technology 6502 The "SO" input pin, when asserted, will set the processor's overflow status bit (deasserting it does not clear the overflow bit, however). This can be used by a high-speed polling device driver, which can poll the hardware once in only three cycles by using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself. For example, the Commodore 1541 and other Commodore floppy disk drives use this technique to detect without delay whether the serializer is ready to accept or provide another byte of disk data. Obviously great care must be used in the device driver and the associated system design, as spurious assertion of the overflow bit could ruin arithmetic processing.
Accelerated Graphics Port To queue a request in-band, the card must request the bus using the standard PCI REQ# signal, and receive GNT# plus bus status ST[2:0] equal to codice_1. Then the card asserts the PIPE# signal while driving the AGP command, address, and length on the C/BE[3:0], AD[31:3] and AD[2:0] lines, respectively. (If the address is 64 bits, a dual address cycle similar to PCI is used.) For every cycle that PIPE# is asserted, the card sends another request without waiting for acknowledgement from the motherboard, up to the configured maximum queue depth. The last cycle is marked by deasserting REQ#, and PIPE# is deasserted on the following idle cycle.